The present invention generally relates to amplifier circuits, and more particularly to a flip-flop type amplifier circuit which is used in a sense amplifier or the like of a semiconductor memory device such as a static random access memory (SRAM) and a dynamic random access memory (DRAM) when amplifying an latching a minute voltage difference between two voltages.
Conventionally, there is a flip-flop type amplifier circuit having a construction shown in FIG. 1. In FIG. 1, a node 1 is supplied with one voltage VIN1, and a node 2 is supplied with another voltage VIN2. A voltage difference between these voltages VIN1 and VIN2 is to be amplified and latched by the flip-flop type amplifier circuit.
A flip-flop circuit 3 includes complementary metal oxide semiconductor (CMOS) inverters 4 and 5. More particularly, the flip-flop circuit 3 includes p-channel MOS transistors (hereinafter simply referred to as pMOS transistors) 6 and 7 which form load elements, and n-channel MOS transistors (hereinafter simply referred to as nMOS transistors) 8 and 9 which form driving elements. In other words, the pMOS transistor 6 and the nMOS transistor 8 form the CMOS inverter 4, and the pMOS transistor 7 and the nMOS transistor 9 form the CMOS inverter 5, and these CMOS inverters 4 and 5 are connected in a ring.
The flip-flop type amplifier circuit also includes a power line 10 for supplying a high voltage side power supply voltage Vcc of 3 V, for example, a pMOS transistor 11 for activating the flip-flop circuit 3, an nMOS transistor 12 for activating the flip-flop circuit 3, an inverter 13, and a node 14. An activation control signal SA for controlling 0N (conducting) and OFF (non-conducting) states of the pMOS transistor 11 and the nMOS transistor 12 to control the activation of the flip-flop circuit 3 is supplied to this node 14.
When the activation control signal SA has the voltage Vcc (high level), the pMOS transistor 11 is ON, the nMOS transistor 12 is ON and the flip-flop circuit 3 is active.
On the other hand, when the activation control signal SA has a voltage of 0 V (low level), the pMOS transistor 11 is OFF, the nMOS transistor 12 is OFF and the flip-flop circuit 3 is inactive.
The flip-flop type amplifier circuit further includes an analog switch 15 made up of a CMOS transfer gate circuit for resetting, and an inverter 16. A reset control signal SB for controlling ON and OFF states of the analog switch 15 is supplied to a node 17.
When the reset control signal SB has a voltage of 0 V, the analog switch 15 is ON and input/output nodes 18 and 19 of the flip-flop circuit 3 are short-circuited.
On the other hand, when the reset control signal SB has the voltage Vcc, the analog switch 15 is OFF and the input/output nodes 18 and 19 of the flip-flop circuit 3 are released from the short-circuited state.
FIG. 2 shows signal waveforms for explaining the operation of the flip-flop type amplifier circuit shown in FIG. 1. FIG. 2 shows the activation control signal SA and the reset control signal SB.
Therefore, according to the flip-flop type amplifier circuit shown in FIG. l, the voltage difference between the voltage VIN1 that is applied to the node 18 via the node and the voltage VIN2 that is applied to the node 19 via the node 2 is amplified and latched. In this case, the activation control signal SA and the reset control signal SB are first respectively set to 0 V.
As a result, the pMOS transistor 11 is turned OFF, the nMOS transistor 12 is turned OFF, and the flip-flop circuit 3 is put into the inactive state. In addition, the analog switch 15 is turned ON, the nodes 18 and 19 are short-circuited, and the potentials of the nodes 18 and 19 become the same, thereby carrying out a resetting operation.
Next, the reset control signal SB is set to the voltage Vcc. Hence, the analog switch 15 is turned OFF, and the short-circuited state between the nodes 18 and 19 is released. As a result, the operation of supplying the voltage VIN1 to the node 18 and supplying the voltage VIN2 to the node 19 is carried out.
Then, the activation control signal SA is set to the voltage Vcc. Thus, the pMOS transistor 11 is turned ON, the nMOS transistor 12 is turned ON, and the flip-flop circuit 3 is put into the active state.
If VIN1&gt;VIN2, for example, the pMOS transistor 6 finally turns ON, the pMOS transistor 7 turns OFF, the nMOS transistor 8 turns OFF and the nMOS transistor 9 turns ON.
Consequently, the potential of the node 18 becomes the voltage Vcc, and the potential of the node 19 becomes 0 V. Accordingly, the potential difference between the voltages VIN1 and VIN2 is amplified, and these voltages are latched during the time when the activation control signal SA has the voltage Vcc.
On the other hand, if VIN1&lt;VIN2, the pMOS transistor 6 finally turns OFF, the pMOS transistor 7 turns ON, the nMOS transistor 8 turns ON and the nMOS transistor 9 turns OFF.
As a result, the potential of the node 18 becomes 0 V, and the potential of the node 19 becomes the voltage Vcc. The potential difference between the voltages VIN1 and VIN2 is amplified, and these voltages are latched during the time when the activation control signal SA has the voltage Vcc.
However, when changing the activation control signal SA from 0 V to the voltage Vcc and starting the latch operation of the flip-flop circuit 3 in the flip-flop type amplifier circuit shown in FIG. 1, there is a time in which the pMOS transistor 11 and the nMOS transistor 12 operate as constant current source circuits. For this reason, an erroneous operation will occur if the voltage difference between the voltages VIN1 and VIN2 is too small.
Such an erroneous operation must be avoided when using the flip-flop type amplifier circuit in a sense amplifier of the SRAM, for example. Hence, it is necessary to delay the timing with which the activation control signal SA is changed from 0 V to the voltage Vcc, that is, the start timing of the latch operation of the flip-flop circuit 3, until the voltage difference between the voltages VIN1 and VIN2 increases to a sufficiently large magnitude that will not cause the erroneous operation. But because of this delay, there was a problem in that a high-speed circuit operation cannot be achieved when this flip-flop type amplifier circuit is used.
The above described problem will be described in more detail by referring to FIGS. 3 and 4 with respect to the nMOS transistor 12, for example.
When changing the activation control signal SA from 0 V to the voltage Vcc, a gate-source voltage V.sub.GS of the nMOS transistor 12 becomes smaller than a drain-source voltage V.sub.DS of the nMOS transistor 12 (that is, V.sub.GS &lt;V.sub.DS) for a predetermined time after the change starts. Hence, during this predetermined time, the nMOS transistor 12 operates as a constant current source circuit for supplying a constant current I.sub.0 as shown in FIG. 3.
If a current flowing through the nMOS transistor 8 is denoted by I.sub.1, a current I.sub.2 flowing through the nMOS transistor 9 becomes I.sub.0 -I.sub.1. Hence, when VIN1&gt;VIN2, fop example, a current that flows through the nMOS transistor 8 is larger by an amount corresponding to an amount the voltage VIN1 is higher than the voltage VIN2. Accordingly, a current that is smaller flows through the nMOS transistor 9 due to the current mirror effect.
As a result, during a time T in which the nMOS transistor 12 operates as the constant current source circuit, the voltage VIN1 falls at a speed higher than that of the voltage VIN2 as shown in FIG. 4. For this reason, if the voltage difference between the voltages VIN1 and VIN2 is too small, the relationship VIN1&gt;VIN2 changes to the relationship VIN1=VIN2 to thereby cause the erroneous operation.
Therefore, when using the above flip-flop type amplifier circuit in the sense amplifier of the SRAM, for example, it is necessary to delay the timing with which the activation control signal SA is changed from 0 V to the voltage Vcc, that is, the start timing of the latch operation of the flip-flop circuit 3, until the voltage difference between the voltages VIN1 and VIN2 increases to a sufficiently large voltage which will not cause the erroneous operation. As described above, this delay prevented the high-speed circuit operation.
In order to eliminate this problem, it is conceivable to connect nMOS transistors 20 and 21 for activating the flip-flop circuit 3 respectively between the source of the nMOS transistor 8 and the ground and between the source of the nMOS transistor 9 and the ground, as shown in FIG. 5. In this case, the nMOS transistors 20 and 21 forms independent current paths, so that the current mirror effect is eliminated. But there still exists a time in which the nMOS transistors 20 and 21 operate as constant current source circuits.
Accordingly, this conceivable arrangement does not require the start timing of the latch operation of the flip-flop circuit 3 to be delayed as much as the flip-flop type amplifier circuit shown in FIG. 1. However, it is still necessary to delay the start timing of the latch operation of the flip-flop circuit 3 by taking into account the time in which the nMOS transistors 20 and 21 operate as the constant current source circuits. Hence, there is a problem in that the circuit operation speed is slowed down by this required timing delay.